It has become commonplace to employ processor components that incorporate one or more relatively high function cores within a computing device. Such higher function cores may incorporate numerous processing features to form a relatively deep pipeline in which multiple executable instructions may be in various stages of execution at the same time. Such higher function cores may also incorporate and/or be coupled to one or more relatively large caches to speed the retrieval and storage of both data and executable instructions as part of ensuring that the next executable instructions to enter into the pipeline for execution are more readily available to the core from within such a cache when needed. Such higher function cores may further employ a relatively sophisticated instruction prefetch algorithm with a relatively sophisticated form of branch prediction to increase the likelihood that the executable instructions available within the cache include the next executable instructions to be executed. However, many of such additions and improvements to the architecture of a high function processor core may be entirely undone as a result of an event that requires a change in a current flow of execution of instructions, such as hardware interrupts and exceptions.